POS SoC Design and Verification

Success Stories

POS SoC Design and Verification

Introduction: This case study showcases Spanidea’s expertise in the design and verification of a Point of Sale (POS) System-on-Chip (SoC). The project involved RTL design and test bench development for a complex SoC targeting multiple POS applications. Spanidea successfully executed tasks such as design, integration, synthesis, LEC (Logic Equivalence Checking), Spyglass, modifications in I/D$, generation of ARM NIC400 using Adcanvas, integration of M0 processor subsystem, architecture and power estimation, and the development of test benches and test cases for peripheral verification at the subsystem and IP levels. The SoC was implemented on 28 nm TSMC technology.

Case Study Overview:

Objective: Design and verify a complex SoC for multiple POS applications, involving RTL design, test bench development, integration, synthesis, LEC, Spyglass, modifications in I/D$, generation of ARM NIC400 using Adcanvas, integration of M0 processor subsystem, architecture and power estimation, and peripheral verification at subsystem and IP levels.

Problem Statement: The client aimed to develop a highly integrated and efficient SoC to power their range of POS systems. They required a comprehensive solution encompassing RTL design, test bench development, integration, synthesis, LEC, Spyglass, modifications in I/D$, generation of ARM NIC400 using Adcanvas, integration of M0 processor subsystem, architecture and power estimation, and peripheral verification at subsystem and IP levels. Spanidea was entrusted with executing these tasks on a 28 nm TSMC technology.

Solution Design: The solution design involved the following key components and technologies:

RTL Design: Spanidea undertook RTL design activities to develop the architecture and logic of the POS SoC, ensuring compatibility with multiple POS applications.
Test Bench Development: Comprehensive test benches were developed to facilitate the verification and validation of the SoC at both the subsystem and IP levels.
Integration: The individual IP blocks and subsystems were integrated into a unified SoC design, enabling seamless functionality and communication among the components.
Synthesis: The SoC design underwent synthesis to optimize its performance, power consumption, and area utilization.
Logic Equivalence Checking (LEC): LEC was performed to ensure functional equivalence between the RTL design and the post-synthesis netlist.
Spyglass: The Spyglass tool was utilized for comprehensive design analysis, ensuring adherence to design guidelines and best practices.
Modifications in I/D$: Modifications were made to the instruction and data caches (I/D$) to improve performance and efficiency.
ARM NIC400 Generation: The ARM NIC400 interface was generated using Adcanvas, enabling seamless connectivity and communication with ARM processor subsystems.
Integration of M0 Processor Subsystem: The M0 processor subsystem was integrated into the SoC design, providing additional processing capabilities.
Architecture and Power Estimation: The SoC design was analyzed to estimate its architecture and power requirements, optimizing performance and power consumption.
Peripheral Verification: Test benches and test cases were developed to verify the functionality and performance of various peripherals at the subsystem and IP levels.

Implementation: The implementation of the POS SoC design and verification involved the following steps:

Requirement Analysis: Detailed discussions and collaboration with the client to understand their POS application requirements, performance goals, and system specifications.
RTL Design and Development: The architecture and logic of the SoC were designed and implemented using RTL design techniques.
Test Bench Development: Comprehensive test benches were developed to validate the functionality and performance of the SoC components at both the subsystem and IP levels.
Integration and Synthesis: The individual IP blocks and subsystems were integrated into a unified SoC design, which underwent synthesis to optimize performance and power consumption.
LEC and Spyglass Analysis: LEC was performed to ensure functional equivalence between the RTL design and the post-synthesis netlist. Spyglass analysis was conducted to ensure design compliance and best practices.
I/D$ Modifications: The instruction and data caches (I/D$) were modified to improve performance and efficiency based on the specific requirements of the POS applications.
ARM NIC400 Generation and Integration: The ARM NIC400 interface was generated using Adcanvas and integrated into the SoC design for seamless connectivity with ARM processor subsystems.
M0 Processor Subsystem Integration: The M0 processor subsystem was integrated into the SoC design, providing additional processing capabilities and versatility.
Architecture and Power Estimation: The SoC design was analyzed to estimate its architecture and power requirements, optimizing performance and power consumption.
Peripheral Verification: Comprehensive test benches and test cases were developed to verify the functionality and performance of various peripherals at the subsystem and IP levels.

Key Features and Benefits:

Comprehensive Integration: The SoC design successfully integrated multiple POS applications, providing a unified and efficient solution.
Improved Performance and Efficiency: Through modifications in I/D$, integration of the M0 processor subsystem, and ARM NIC400 generation, the SoC achieved improved performance, processing capabilities, and power efficiency.
Enhanced Validation: The development of comprehensive test benches and test cases enabled thorough validation of the SoC design, ensuring functionality and performance at the subsystem and IP levels.
Design Compliance and Best Practices: The use of LEC and Spyglass analysis ensured design compliance, adherence to guidelines, and implementation of industry best practices.
Optimized Architecture and Power Consumption: Architecture and power estimation analysis contributed to an optimized SoC design, balancing performance with power consumption.
Streamlined Development Processes: Spanidea’s expertise in RTL design, test bench development, integration, synthesis, LEC, and Spyglass enabled streamlined development processes, ensuring efficient execution and timely delivery.

Results and Impact:

Successful SoC Development: The POS SoC design and verification project was successfully executed by Spanidea, resulting in a highly integrated and efficient SoC solution for multiple POS applications.
Improved POS System Performance: The developed SoC contributed to improved performance and efficiency of the client’s POS systems, enhancing overall user experience.
Time and Cost Savings: Spanidea’s expertise and streamlined development processes resulted in significant time and cost savings for the client, accelerating their time-to-market and reducing development expenses.
Enhanced Competitive Advantage: The comprehensive POS SoC solution provided the client with a competitive edge, offering advanced features, optimized performance, and seamless integration for their POS systems.
Long-Term Collaboration: The successful execution of the project fostered a long-term collaboration between the client and Spanidea, ensuring ongoing support, maintenance, and future development opportunities.